1. Field of the Invention
The present invention relates to a semiconductor device having N- and P-channel MOS transistors and a method of manufacture thereof. More specifically, the present invention relates to a semiconductor device in which MOS transistors have their active regions connected by an interconnect layer and a method of manufacture thereof.
2. Description of the Related Art
The demand has increased for enhancing the performance of LSI devices. In semiconductor process technology, on the other hand, advanced fine pattern techniques have been increasingly needed. Under these circumstances, it is essential to increase further the packing densities of LSI devices and, to this end, it is required to scale down the dimensions of devices as much as possible.
LSI devices contain many interconnect patterns for electrically connecting adjacent regions, for example, n- and p-type regions. In this case, the n- and p-type regions are isolated from each other by a shallow trench isolation region (hereinafter referred to as an STI) and electrically connected with each other by an overlying metal line.
SRAMs (Static Random Access Memories) contain interconnect patterns, called local interconnects, for interconnection of sources, gate electrodes and drains of MOS transistors. The method of forming the local interconnects involves forming a large opening in an interlayer dielectric film above the sources, gate electrodes and drains and filling the opening with a conductive material.
FIG. 1 is a sectional view of a conventional semiconductor device that has local interconnects. As shown in FIG. 1, the device has a p-type substrate 51. In the substrate 51 a p-type well region 52 and an n-type well region 53 are provided. In the p-type well region 52, n-type regions 55 are formed, which will be processed to provided the source and drain of an n-channel MOS transistor 54. In the n-type well region 53, p-type regions 57 are formed, which will be processed to provide the source and drain of a p-channel MOS transistor 56. An STI 58 is formed in the substrate 51 to isolate the MOS transistors 52 and 53 from each other. A gate electrode 59 is formed above a portion of the substrate between the paired n-type regions 55 of each of the MOS transistors 52 and a gate electrode 59 is formed above a portion of the substrate between the paired p-type regions 57 of the MOS transistor 53. A gate electrode 59 of another device is also formed above the STI 58. An interlayer dielectric film 60 is formed over the entire surface. An opening 61 is formed in the interlayer dielectric film 60 so that a portion of the n-type region 55 and the p-type region 57 on the STI side of each of the MOS transistors 54 and 56 and the gate electrode 59 above the STI 58 are exposed. A local interconnect is formed by filling the opening 61 with a conductive material 62.
To manufacture the semiconductor device of FIG. 1, the opening 61 is made by means of reactive ion etching (RIE). That part of STI 58 that contacts the diffusion region is inevitably etched away. A leakage current will flow between the local interconnect and the substrate.
A conventional semiconductor device having local interconnects is described in Japanese Unexamined Patent Publication No. 2000-114262. With this semiconductor device, paired active regions isolated by an STI are connected together by an interconnect line, which is formed through the use of selective growth and selective etching techniques for silicon.
As FIG. 2 shows, the p-type well region 52 and the n-type well region 53 are provided in the surface of the p-type substrate 51. As described above, the n-type region 55 and the p-type region 57 are formed in the p-type well region 52 and the n-type well region 53, respectively. As specified above, too, the n-type region 55 will be processed to provided the source and drain of an n-channel MOS transistor 54, and the p-type region 57 will be processed to provide the source and drain of a p-channel MOS transistor 55. A film of amorphous silicon is deposited over the entire surface of the substrate and then subjected to a selective growth operation to form a film of monocrystalline silicon. After that, the amorphous silicon film in areas other than the interconnect-to-be-formed area is removed with the result that an interconnect 63 consisting of a silicide film is left in the interconnect-to-be-formed area. This interconnect 63 is formed across the STI 58.
With the semiconductor device shown in FIG. 2, there is no need of etching an interlayer dielectric film to form an opening, preventing leakage current occurring between the interconnect and the substrate as a result of the substrate being etched.
However, it is very difficult to leave the silicide film forming the interconnect 63 in a desired pattern.
The conventional semiconductor device is advantageous, however. A junction leakage current may flow when the diffusion regions isolated from one another by the isolation regions are connected by interconnect layers. Further, it is difficult to form the interconnect layers.